IA-32 Module
The IA-32 POST codes all have the Most Signicant Bit (MSB) cleared by the convention established
above in this document. The IA-32 POST codes do not fall into the module denition for Itanium
®
-
based platforms. The codes shown here are consistent with the 7.0 AMI core.
Table 39. IA-32 POST Codes
Code Value Module Display
0x00D0 Power-on delay is starting. Next, the initialization code checksum will
be verified.
South
0x00D1 Initializing the DMA controller, performing the keyboard controller
BAT test, starting memory refresh, and entering 4GB flat mode next.
South
0x00D3 Starting memory sizing next. South
0x00D4 Returning to real mode. Executing any OEM patches and setting up
the stack next.
South
0x00D5 Passing control to the uncompressed code in shadow RAM at E000
0000h.The initialization code is copied to segment 0 and control will
be transferred to segment 0.
South
0x00D6 Control is in segment 0. If the system BIOS checksum is bad, next will
go to checkpoint code E0h. Otherwise, going to checkpoint code D7h.
South
0x00D7 Passing control to the interface module next. South
0x00D8 The main system BIOS runtime code will be decompressed next. South
0x00D9 Passing control to the main system BIOS in shadow RAM next. South
0x0003 Next, checking for a soft reset or a power on condition. South
0x0005 The BIOS stack has been built. Next, disabling cache memory. South
0x0006 Uncompressing the POST code next. South
0x0008 The CMOS checksum calculation is done next. South
0x000B Next, performing any required initialization before the keyboard BAT
command is issued.
South
0x000C The keyboard controller input buffer is free. Next, issuing the BAT
command to the keyboard controller.
South
0x000E The keyboard controller BAT command result has been verified. Next,
performing any necessary initialization after the keyboard controller
BAT command test.
South
0x000F The initialization after the keyboard controller BAT command test is
done. The keyboard command byte is written next.
South
0x0010 The keyboard controller command byte is written. Next, issuing the
Pin 23 and 24 blocking and unblocking commands.
South
0x0011 Check for INS key pressed. Get POST info. South
0x0012 Disable DMA controllers 1 and 2 and interrupt controllers 1 and 2. South
0x0013 The video display has been disabled. Next, initializing the chipset. South
0x0014 The 8254 timer test will begin next. South
0x0019 The 8254 timer test is over. Starting the memory refresh test next. South
0x001A The memory refresh line is toggling. Checking the 15-second on/off
time next.
South
0x0023 Reading the 8042 input-port and disabling the MEGAKEY Green PC
feature next. Making the BIOS code segment writable and performing
any necessary configuration before initializing the interrupt vectors.
South
continued
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